1. Field of the Invention
The present invention relates generally to direct digital synthesis.
2. Description of the Related Art
Direct digital synthesis (DDS) utilizes digital processing to generate output signals whose stability is referenced to a precision clock and whose frequency and phase are tunable. An exemplary conventional DDS generator 20 is shown in FIG. 1A. It includes a phase accumulator 22 and a phase-to-amplitude (xcfx86-A) converter 24 that both receive a clock signal fclk from a system clock 25.
The phase accumulator 22 is basically a modulo xcfx86s digital N-bit counter that counts at a rate fclk wherein xcfx86s is a phase step that is provided to the phase accumulator at a generator port 26. Accordingly, the phase accumulator delivers a periodic stream of digital works over a circuit path 27 to the xcfx86-A converter 24.
This operation can be illustrated with reference to a digital phase wheel 30 of FIG. 1B. As exemplified by successive radial rays 31A, 31B, 31C, 31D and 31E in this wheel, the phase accumulator repetitively counts around the wheel perimeter 32 (e.g., from an initial N-bit digital word 0000 . . . 0 to a final N-bit digital word 1111 . . . 1) to form the periodic stream of digital words. As further indicated in association with a process direction arrow 33, the N-bit phase accumulator 22 of FIG. 1A has a word capacity C=2N so that it generates a periodic stream of digital words over the circuit path 27 with a period P=C/(xcfx86s fclk). Stated differently, the phase accumulator 22 places digital words on the circuit path 27 at a rate of fclk and the periodic stream of words repeats at an output frequency of fout=(xcfx86s fclk)/C.
FIG. 1B appears to indicate that the phase step xcfx86s moves only between adjacent digital words 34. It should be understood, however, that FIG. 1B would need to show 268,435,456 digital words along its perimeter 32 to completely illustrate the operation of an exemplary 28-bit phase accumulator. Because of illustrative limits, such word density cannot be shown in the figures and, accordingly, the enlarged view of FIG. 1C indicates that additional words 36 may be located between each adjacent pair of the words 34 of FIG. 1Bxe2x80x94the number of the additional words being a function of the size of the selected phase step xcfx86s.
The periodic stream of digital words on the circuit path 27 of FIG. 1A includes a repetitive sequence from 000 . . . 0 to 111 . . . 1. This sequence expresses a linear relationship and, accordingly, a periodic analog ramp would be generated if the periodic stream were fed directly to a digital-to-analog converter (DAC). Therefore, the DDS generator 20 includes a xcfx86-A converter 24 which converts the digital words at respective phase locations to converted digital words at the generator output port 28 wherein the converted digital words represent respective amplitudes of any predetermined waveform (e.g., a sinusoidal waveform). A DDS synthesizer may then be realized by coupling a DAC to the generator output port 28.
When compared to other waveform synthesis techniques (e.g., phase-locked loop synthesis), DDS offers a number of attractive features which include:
a) extremely fine tuning resolution of the output frequency fout,
b) fast change of output phase and fast phase-continuous change of output frequency fout;
c) generation of multiple phase-related periodic streams,
d) performance that is not affected by component changes (due, for example, to aging and temperature),
e) remote control (e.g., by digital processors), and
f) integrated structure on a single chip (including an output DAC).
It is apparent that the output frequency fout of the DDS generator 20 can only be increased with a corresponding increase in the rate fclk at which the phase accumulator 22 and xcfx86-A converter 24 operate. This rate, however, is limited by the DDS generator""s fabrication process. Complementary metal-oxide semiconductor (CMOS) processes, for example, are characterized by the minimum gate length (e.g., 0.25 microns) they can achieve and this gate length sets an upper bound on the operating rate of devices fabricated with the process.
In addition to this absolute limit, attempts to increase the operating rate fclk face other problems such as higher current slew rates, tighter timing requirements and the need for more extensive signal pipelining. As a result, circuit complexity and power dissipation are increased and larger device geometries are required. It is apparent, therefore, that substantial benefits would be realized with methods and structures that increased DDS output frequencies fout without requiring a corresponding increase in the operating rate fclk.
The present invention is directed to DDS methods and structures that increase DDS output frequencies fout without requiring a corresponding increase in the rate fclk at which DDS structures must operate.
An exemplary method of the invention generates a periodic stream of digital words at a clock frequency fclk wherein the words represent respective amplitudes of a predetermined periodic waveform, the periodic stream has a period P and the digital words are spaced by a phase step xcfx86s. The method comprises the steps of:
a) with a count capacity C, counting modulo nxcfx86s at a reduced clock frequency (1/n)fclk to thereby generate a primary substream of digital words;
b) phase offsetting the primary substream to form nxe2x88x921 secondary substreams of digital words wherein the primary and secondary substreams are phase spaced by the phase step xcfx86s;
c) converting the digital words of each of the primary and secondary substreams to converted digital words that represent respective amplitudes of the predetermined waveform; and
d) interleaving the primary and secondary substreams to thereby form the periodic stream of digital words that occur at the clock frequency fclk.
These process steps can be practiced with any integer n and they form a multiphase, interleaved method that generates a periodic stream of digital words that occur at a clock frequency fclk but realizes this stream with counting, offsetting and converting processes that are realized at a substantially reduced frequency (1/n)fclk. Therefore, significant improvements in DDS operational parameters (e.g., decrease of current slew rates, decrease of data pipelining, reduced circuit complexity and power dissipation and smaller device geometries) are realized.
DDS generator and synthesizer embodiments are also provided for practicing the methods of the invention.